Many moons ago when I owned a ZX80, I remember (or possibly mis-remember) seeing a simple way to double the RAM to 2K by simply piggy-backing two extra 1Kx4 chips on top of the existing two (with pin-to-pin solder), for all pins bar the chip select (CS).
CS on the new piggy-backed chips would be "bent out" and sourced from a small circuit which would only be set for the 1K-2K range.
However, from circuit diagrams found on Grant Searle's excellent pages, it looks like current CS is set by taking the NAND of [MREQ']' and A14', meaning every address in the 16-32K and 48-64K ranges selects those original RAM chips (with 0-16K and 32-48K presumably being reserved for ROM):
Given only the lower ten address lines are delivered to the RAM chips, this has the effect of duplicating the 1K RAM at every 1K boundary in those ranges (so the same data would exist at 4000, 4400, 4800, ... 7C00, C000, C400, ... FC00)(1).
So my question starts with: how did the 16K RAM expansion handle this without cutting the CS feeds (the actual solder tracks) to the existing RAM chips? Having both the internal and external RAM pushing bits on to the data bus for certain addresses would surely result in much hilarity :-)
The RAM CS signal is sent to the expansion port but I can't figure out how, when a memory board was plugged in, it would somehow prevent the internal RAM from responding to some addresses (or all addresses if it was replaced by the expansion RAM rather than augmented by it).
My original thought on how to do it with the piggy back method would be to take the current RAM CS and combine that with A10 so that it only selected the new RAM for alternate 1K regions of the RAM areas.
But that means I would have to similarly modify the CS for the old RAM so that it didn't select on those same regions. In other words, the current RAM CS would have to be processed something like this (apologies for the "graphics"):
RAM CS ──┬─────────┐│ (and) ── CS[NEW] A10 ─[│]───┬────┘│ (not)│└────┐│ (and) ── CS[OLD]└─────────┘That would require cutting tracks on the motherboard to change how the old RAM was selected because, currently, RAM CS feeds directly into CS[OLD].
So maybe there's another way if the RAM pack can do it. Though, if it requires replacing on-board RAM then, obviously, piggy-backing 1K will not be enough as that would simply replace the current 1K with a different 1K.
So the second (and final) part of my question is: how feasible is this piggy back approach, either with:
- trying to figure out how to piggy-back a couple of 2Kx4 chips to replace onboard memory (so I'd need a separate
A10line to the new chips and a way to disable existing RAM); or - using the "cut the trace" method to augment the existing 1K with another 1K?
(1) It's fun figuring out the tricks used to keep the costs down for this and other hardware of the era. Though I still think that the ZX80 "execute the display file" and Woz's brilliant Apple II RWTS routines put a lot of other things to shame :-)